SH7058 Datasheet, PDF (303/1130 Pages) Renesas Technology Corp – Renesas SuperHTM RISC engine

• Bit 2—Input Capture/Compare-Match Flag 1C (IMF1C): Status flag that indicates GR1C input
capture or compare-match.
Bit 2: IMF1C
0
1
Description
[Clearing condition]
(Initial value)
When IMF1C is read while set to 1, then 0 is written to IMF1C
[Setting conditions]
• When the TCNT1A value is transferred to GR1C by an input capture
signal while GR1C is functioning as an input capture register
• When TCNT1A = GR1C while GR1C is functioning as an output compare
register
• Bit 1—Input Capture/Compare-Match Flag 1B (IMF1B): Status flag that indicates GR1B input
capture or compare-match.
Bit 1: IMF1B
0
1
Description
[Clearing condition]
(Initial value)
When IMF1B is read while set to 1, then 0 is written to IMF1B
[Setting conditions]
• When the TCNT1A value is transferred to GR1B by an input capture
signal while GR1B is functioning as an input capture register
• When TCNT1A = GR1B while GR1B is functioning as an output compare
register
• Bit 0—Input Capture/Compare-Match Flag 1A (IMF1A): Status flag that indicates GR1A
input capture or compare-match.
Bit 0: IMF1A
0
1
Description
[Clearing condition]
(Initial value)
When IMF1A is read while set to 1, then 0 is written to IMF1A
[Setting conditions]
• When the TCNT1A value is transferred to GR1A by an input capture
signal while GR1A is functioning as an input capture register
• When TCNT1A = GR1A while GR1A is functioning as an output compare
register
Rev. 3.0, 09/04, page 262 of 1086