SH7058 Datasheet, PDF (931/1130 Pages) Renesas Technology Corp – Renesas SuperHTM RISC engine

CPU cycle
CPU operation for instruction
that sets SCO bit to 1
n
Fetch
n+1
Decoding
n+2
Execution
n+3
Execution
n+4
Execution
Interrupt acceptance
(a)
(b)
(c)
(a) When the interrupt is accepted at or before the (n + 1) cycle
After the interrupt processing completes, the SCO bit is set to 1 and download is executed.
(b) When the interrupt is accepted at the (n + 2) cycle
The interrupt conflicts with the SCO download request. For details on operation in this case, see
2. Operation when contention occurs.
(c) When the interrupt is accepted at or after the (N + 3) cycle
The SCO download request occurs prior to the interrupt request, and download is executed.
During download, no other interrupt processing can be handled. If an interrupt is still being
requested after download completes, the interrupt processing starts. For details on interrupt
requests during download, see 3. Interrupt requests generated during download.
Figure 23.21 Timing of Contention between SCO Download Request and Interrupt Request
2. Operation when contention occurs
Operation differs according to the type of interrupt with which the SCO download request
has conflicted.
 NMI, UBC, and H-UDI interrupt requests
Operation for when these interrupts conflict with the SCO download request is described
below.
Main processing
Contention between
SCO and interrupt
SCO download
processing
Interrupt processing,
e.g. NMI
Figure 23.22 Contention between Interrupts (e.g. NMI)
Rev. 3.0, 09/04, page 890 of 1086