SH7058 Datasheet, PDF (538/1130 Pages) Renesas Technology Corp – Renesas SuperHTM RISC engine

Initialization
1
Start of reception
Read ORER, PER, and
FER bits in SSR
PER, FER,
ORER = 1?
No
Yes
2
Error handling
Read RDRF bit in SSR
3
No
RDRF = 1?
Yes
Read receive data in RDR and
clear RDRF bit in SSR to 0
4
No
All data received?
Yes
Clear RE bit in SCR to 0
1. SCI initialization: Set the RxD pin using the
PFC.
2. Receive error handling and break detection:
If a receive error occurs, read the ORER,
PER, and FER bits of SSR to identify the
error. After executing the necessary error
handling, clear ORER, PER, and FER all to
0. Receiving cannot resume if ORER, PER
or FER remain set to 1. When a framing
error occurs, the RxD pin can be read to
detect the break state.
3. SCI status check and receive-data read:
Read the serial status register (SSR), check
that RDRF is set to 1, then read receive
data from the receive data register (RDR)
and clear RDRF to 0. The RXI interrupt can
also be used to determine if the RDRF bit
has changed from 0 to 1.
4. Continue receiving serial data: Read RDR
and the RDRF bit and clear RDRF to 0
before the stop bit of the current frame is
received. If the DMAC is started by a
receive-data-full interrupt (RXI) to read
RDR, the RDRF bit is cleared automatically
so this step is unnecessary.
End of reception
Figure 15.7 Sample Flowchart for Receiving Serial Data (1)
Rev. 3.0, 09/04, page 497 of 1086