SH7058 Datasheet, PDF (627/1130 Pages) Renesas Technology Corp – Renesas SuperHTM RISC engine

Bit
Bit Name Initial Value R/W Description
5
TCR5
0
R/W HCAN-II Timer Prescaler
4
TCR4
0
3
TCR3
0
2
TCR2
0
1
TCR1
0
0
TCR0
0
R/W Divide the source clock (2 • HCAN peripheral

clock) before it is used for the timer. The following
relationship exists between source clocks and the

timer

000000: 1 • source clock

000001: 2 • source clock
000010: 4 • source clock
000011: 6 • source clock
000100: 8 • source clock
:
111111: 126 • source clock
16.6.3 Timer Status Register_n (TSR_n) (n = 0, 1)
The timer status register (TSR) is a 16-bit read-only register that allows the host CPU to monitor
the timer compare match status and the timer overrun status.
Bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TSR TSR TSR TSR TSR
43210
Initial Value: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
R/W:            R R R R R
Bit
Bit Name
15 to 5 —
Initial Value R/W
0

4 to 0 TSR[4:0] 0
R
Description
Reserved
Writing 0 to this bit is ignored. The read value is
not guaranteed.
These bits are read-only that allow the CPU to
monitor the status of the cycle counter, the timer,
and the compare match registers. Writing to these
bits is ignored.
Rev. 3.0, 09/04, page 586 of 1086