SH7058 Datasheet, PDF (596/1130 Pages) Renesas Technology Corp – Renesas SuperHTM RISC engine

16.4.5 Interrupt Register_n (IRR_n) (n = 0, 1)
The interrupt register (IRR) is a 16-bit readable/writable register that contains status flags for the
various interrupt sources.
• IRR
Bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IRR IRR IRR IRR IRR IRR IRR9 IRR8 IRR7 IRR6 IRR5 IRR4 IRR3 IRR2 IRR1 IRR0
15 14 13 12 11 10
Initial Value: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1
R/W: R/W R/W R/W R/W R/W R/W R R R/W R/W R/W R/W R/W R R R/W
Bit
Bit Name Initial Value R/W Description
15
IRR15
0
R/W Timer Compare Match Interrupt Flag 1
Indicates that a compare-match condition
occurred to the timer compare match register 1
(TCMR1). When the value set in TCMR1 matches
the timer value (TCMR1 = TCNTR), this bit is set.
This bit is not set if the TCMR1 value is H'0000.
0: Timer compare match has not occurred to
TCMR1
Clearing condition: Writing 1
1: Timer compare match has occurred to TCMR1
Setting condition: TCMR1 matches the timer
value (TCMR1 = TCNTR) if TMR1 = 0 or
matches Cycle_Count + TCNTR[15:4] if TMR1
=1
14
IRR14
0
R/W Timer Compare Match Interrupt Flag 0
Indicates that a compare-match condition
occurred to the timer compare match register 0
(TCMR0). When the value set in TCMR0 matches
the timer value (TCMR0 = TCNTR), this bit is set.
This bit is not set if the TCMR0 value is H'0000.
0: Timer compare match has not occurred to the
TCMR0
Clearing condition: Writing 1
1: Timer compare match has occurred to the
TCMR0
Setting condition: TCMR0 matches the timer
value (TCMR0 = TCNTR)
Rev. 3.0, 09/04, page 555 of 1086