SH7058 Datasheet, PDF (35/1130 Pages) Renesas Technology Corp – Renesas SuperHTM RISC engine

18.2.7 A/D Duty Registers A and B (ADDR0A, ADDR0B, ADDR1A,
and ADDR1B) ..................................................................................................... 665
18.3 Interrupt Interface ............................................................................................................. 666
18.3.1 On-Chip Peripheral Module Interrupts ................................................................ 666
18.3.2 Interrupt Exception Vectors and Priority Rankings ............................................. 666
18.3.3 Interrupt Priority Registers A–L (IPRA–IPRL) ................................................... 675
18.4 PFC and I/O Port Interfaces .............................................................................................. 677
18.4.1 PFC Interface ....................................................................................................... 677
18.4.2 Port A Control Registers H and L (PACRH, PACRL) ........................................ 677
18.4.3 I/O Port A............................................................................................................. 681
18.5 Operation .......................................................................................................................... 682
18.5.1 Overview.............................................................................................................. 682
18.5.2 PWM Operation ................................................................................................... 683
18.5.3 Compare Match Operation................................................................................... 683
18.5.4 Multi-Trigger A/D Conversion Operation ........................................................... 683
18.5.5 Interrupts.............................................................................................................. 688
18.5.6 Usage Notes ......................................................................................................... 689
18.5.7 Operation Waveform Examples........................................................................... 689
18.6 Appendices........................................................................................................................ 692
18.6.1 On-Chip Peripheral Module Registers ................................................................. 692
18.6.2 Pin States.............................................................................................................. 693
18.6.3 AC Characteristics ............................................................................................... 693
Section 19 High-performance User Debug Interface (H-UDI) ........................695
19.1 Overview........................................................................................................................... 695
19.1.1 Features................................................................................................................ 695
19.1.2 H-UDI Block Diagram......................................................................................... 696
19.1.3 Pin Configuration................................................................................................. 697
19.1.4 Register Configuration......................................................................................... 697
19.2 External Signals ................................................................................................................ 698
19.2.1 Test Clock (TCK) ................................................................................................ 698
19.2.2 Test Mode Select (TMS)...................................................................................... 698
19.2.3 Test Data Input (TDI) .......................................................................................... 698
19.2.4 Test Data Output (TDO) ...................................................................................... 698
19.2.5 Test Reset (TRST) ............................................................................................... 699
19.3 Register Descriptions ........................................................................................................ 699
19.3.1 Instruction Register (SDIR) ................................................................................. 699
19.3.2 Status Register (SDSR)........................................................................................ 701
19.3.3 Data Register (SDDR) ......................................................................................... 702
19.3.4 Bypass Register (SDBPR) ................................................................................... 702
19.3.5 Boundary scan register (SDBSR)......................................................................... 702
19.3.6 ID code register (SDIDR) .................................................................................... 719
19.4 Operation .......................................................................................................................... 720
Rev. 3.0, 09/04, page xxxii of xxxviii