SH7058 Datasheet, PDF (583/1130 Pages) Renesas Technology Corp – Renesas SuperHTM RISC engine

16.4.1 Register Descriptions
Legends for register descriptions are as follows:
Initial Value
—
R/W
R
R/WC0
R/WC1
W
—/W
: Register value after a reset
: Undefined value
: Readable/writable bit. The write value can be read.
: Read-only bit. The write value should always be 0.
: Readable/writable bit. If 0 is written to this bit, the bit is initialized; if 1 is written
to this bit, it is ignored.
: Readable/writable bit. If 1 is written to this bit, the bit is initialized; if 0 is written
to this bit, it is ignored.
: Write-only bit. Reading prohibited. If reserved, the write value should always be
0.
: Write-only bit. The read value is undefined.
16.4.2 Master Control Register_n (MCR_n) (n = 0, 1)
The master control register (MCR) is a 16-bit readable/writable register that controls the HCAN.
Bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TST TST TST TST TST TST TST TST MCR
765432107
MCR MCR
54
MCR MCR MCR
210
Initial Value: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1
R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W  R/W R/W  R/W R/W R/W
Bit
Bit Name Initial Value R/W Description
15
TST7
0
R/W Test Mode
Enables/disables the test modes settable by
TST[6:0]. When this bit is set, the following TST[6:0]
are enabled.
0: HCAN is in normal mode
1: HCAN is in test mode
14
TST6
0
R/W Write CAN Error Counters
Enables the TEC (transmit error counter) and REC
(receive error counter) to be writable. The same
value is written to TEC and REC at the same time.
The maximum value that can be written to TEC and
REC is D'255 (H'FF). This means that the HCAN
cannot be forced into the bus off state. Before
writing to TEC and REC, the HCAN needs to enter
halt mode, and when writing to TEC and REC, the
TST7 bit (MCR15) should be set to 1. The value
written to TEC is used to write REC.
0: TEC/REC is not writable but read-only
Rev. 3.0, 09/04, page 542 of 1086