SH7058 Datasheet, PDF (177/1130 Pages) Renesas Technology Corp – Renesas SuperHTM RISC engine

A user break interrupt will occur before the instruction at address H'00000404. If it is possible
for the instruction at H'00000402 to accept an interrupt, the user break exception processing
will be executed after execution of that instruction. The instruction at H'00000404 is not
executed. The PC value saved is H'00000404.
2. Register settings: UBARH = H'0015
UBARL = H'389C
UBBR = H'0058
UBCR = H'0000
Conditions set:
Address: H'0015389C
Bus cycle: CPU, instruction fetch, write
(operand size not included in conditions)
Interrupt requests enabled
A user break interrupt does not occur because the instruction fetch cycle is not a write cycle.
3. Register settings: UBARH = H'0003
UBARL = H'0147
UBBR = H'0054
UBCR = H'0000
Conditions set:
Address: H'00030147
Bus cycle: CPU, instruction fetch, read
(operand size not included in conditions)
Interrupt requests enabled
A user break interrupt does not occur because the instruction fetch was performed for an even
address. However, if the first instruction fetch address after the branch is an odd address set by
these conditions, user break interrupt exception processing will be carried out after address
error exception processing.
8.4.2 Break on CPU Data Access Cycle
1. Register settings: UBARH = H'0012
UBARL = H'3456
UBBR = H'006A
UBCR = H'0000
Conditions set:
Address: H'00123456
Bus cycle: CPU, data access, write, word
Interrupt requests enabled
A user break interrupt occurs when word data is written into address H'00123456.
2. Register settings: UBARH = H'00A8
UBARL = H'0391
UBBR = H'0066
UBCR = H'0000
Rev. 3.0, 09/04, page 136 of 1086