SH7058 Datasheet, PDF (631/1130 Pages) Renesas Technology Corp – Renesas SuperHTM RISC engine

16.6.5 Timer Drift Correction Register n (TDCRn) (n = 0, 1)
The timer drift correction register (TDCR) is a 16-bit readable/writable register. The purpose of
this register is to adjust the drift of the timer caused by a different clock running at other CAN
nodes on the same system. When TCNTR reaches to the cycle specified by this register, the timer
value is incremented by 2 or 0 (i.e. retains the same value). This register does not point at a
specific time nor a specific cycle. This means, if TCNTR/2 > TDCR, the drift correction will be
performed more than twice (unless TCMR0 is used to clear TCNTR before it reaches the second
cycle). When TDCR is set to H'0000, the drift correction will not be performed at all.
Bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TDCR[15:0]
Initial Value: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
R/W: R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Bit
Bit Name
15 to 0 TDCR[15:0]
Initial Value R/W
0
R/W
Description
Timer Drift Correction Register
Set the value of the cycle to adjust the drift of
the timer.
Important: For a proper operation of the
timer, the maximum value must be TDCR <=
8000 (hexadecimal).
16.6.6 Local Offset Register n (LOSRn) (n = 0, 1)
The local offset register (LOSR) is a 16-bit readable/writable register that sets a local offset value
to TCNTR. When TCNTR is cleared by an overflow, timer compare match, or CAN-ID compare
match, TCNTR starts running at the value set in this register.
Bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LOSR[15:0]
Initial Value: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
R/W: R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Bit
Bit Name
15 to 0 LOSR[15:0]
Initial Value R/W
0
R/W
Description
Local Offset Register
Indicate the value of the local offset for
TCNTR to start with.
Rev. 3.0, 09/04, page 590 of 1086