SH7058 Datasheet, PDF (14/1130 Pages) Renesas Technology Corp – Renesas SuperHTM RISC engine

Item
16.3.2 Message Control Field
Page Revisions (See Manual for Details)
533-
534,
537
MBx[4], MBx[5]* H'104 + N x 32 6 TCT
Timer Counter Transfer
When this bit is set, a mailbox is set for
transmission, and the DLC is set to 4, the
TCNTR value, at the SOF, is embedded
in the second and third bytes of the
message data, instead of MSG_DATA_2
and MSG_DATA_3, and the
CYCLE_COUNT in the first byte instead
of MSG_DATA_0[3:0] when this mailbox
starts transmission.
This function will be useful when the
HCAN performs a time master role to
transmit the time reference message.
For example, considering that two HCAN
controllers are connected in the same
network and that the receiver stores the
message in mailbox N, the data format is
shown as figure 16.4 depending on the
endian setting for the CAN bus (MCR4).
Important: This function is not supported
by the SH7058.
Thus the write value should be 0.
The value read as the initial value is not
guaranteed.
MBx[4], MBx[5]* H'104 + N x 32 5 CBE
4 CLE
CAN Bus Error
An external fault-tolerant CAN
transceiver can be used together with the
HCAN module. If the error output pin of
the transceiver (normally active low) is
connected to the CAN_NERR pin of this
LSI, the value of the CAN_NERR pin is
stored into this bit at the end of each
transmission/reception (if the message is
stored). The inverted value of the
CAN_NERR pin is set to this bit. If the
error output pin is active high, the setting
value is not inverted. When this bit is set,
it indicates a potential physical error with
the CAN bus. As the CAN_NERR value
is updated after the transmission or
reception in the corresponding mailbox,
non-interrupt is dedicated to this function
but instead the normal transmit end
interrupt (IRR6) and normal receive end
interrupt (IRR2) should be considered.
Important: This function is not supported
by the SH7058. Thus the write value
should be 0. The value read as the initial
value is not guaranteed.
Transmit Clear Enable
When this bit is set, message reception
in the corresponding mailbox cancels the
wait messages in the transmission
queue. This action is notified by IRR8
and ABACK.
Important: This function is not supported
by the SH7058. Thus the write value
should be 0. The value read as the initial
value is not guaranteed.
MBx[6]*
H'106 + N x 32
15 TimeStamp Message Reception:
to 0 [15:0]
During message reception, when the
SOF or EOF is detected, ICR1 (input
capture register 1) always captures the
TCNTR (timer counter register) value or
the value of Cycle_Counter +
TCNTR[15:4], depending on the value of
bit 3 in TMR (Timer mode register), at
either SOF or EOF depending on the
value in TCR13 (timer control register),
and the ICR1 value is stored into the
timestamp field of the corresponding
mailbox.
Important: Capturing at the SOF is not
supported by the SH7058. Thus TCR13
should be set to EOF detection mode.
Message Transmission:
During message transmission, the
TCNTR (timer counter register) value or
the value of Cycle_Counter +
TCNTR[15:4], depending on the value
of bit 3 in TMR (timer mode register) is
captured when either the TXPR bit or
TXACK bit is set depending on the value
in TCR12, and the captured value is
stored into the timestamp field of the
corresponding mailbox.
Important: Capturing when the TXPR bit
is set is not supported by the SH7058.
Activation of the TCNR (timer) causes a
problem in the SH7058 (timer usage is
prohibited). Therefore, the timestamp
function is not supported.
The write value should be 0. The value
read as the initial value is not
guaranteed.
Rev. 3.0, 09/04, page xi of xxxviii