SH7058 Datasheet, PDF (598/1130 Pages) Renesas Technology Corp – Renesas SuperHTM RISC engine

Bit
Bit Name Initial Value R/W Description
10
IRR10
0
R/W Cycle Counter Overrun Interrupt Flag
Indicates that the Cycle_Counter has reached the
maximum value (CMAX). When the CCR counter
matches the CMAX value (CCR = CMAX), this bit
is set and CCR is cleared. Note that setting
CMAX = 0 disables the Cycle_Counter and no
interrupt is generated.
0: Cycle counter has not reached CMAX or CMAX
=0
Clearing condition: Writing 1
1: Cycle counter has reached CMAX and CMAX ≠
0
Setting condition: CCR matches the CMAX
value (CCR = CMAX)
9
IRR9
0
R
Message Overrun/Overwrite Interrupt Flag
Status flag indicating that new message has been
received but the existing message in the mailbox
has not been read due to the corresponding
RXPR or RFPR set to 1. The received message is
either abandoned (overrun) or overwritten
dependant upon the NMC (new message control)
bit. This bit is cleared by writing 1 to the
correspondent bit in UMSR (unread message
status register). Writing 0 is ignored.
0: No message overrun/overwrite
Clearing condition: Clearing of all bits in UMSR
1: Receive message overrun and its storage has
been rejected or message overwrite
Setting condition: Message is received while
the corresponding RXPR or RFPR = 1 and
MBIMR = 0
Rev. 3.0, 09/04, page 557 of 1086