SH7058 Datasheet, PDF (459/1130 Pages) Renesas Technology Corp – Renesas SuperHTM RISC engine

Halting of a Down-Counter by the CPU: A down-counter (DCNT) can be halted by writing
H'0000 to it. The CPU cannot write 0 directly to the down-count start register (DSTR); instead, by
setting DCNT to H'0000, the corresponding DSTR bit is cleared to 0 and the count is stopped.
However, the OSF bit in the timer status register (TSR) is set when DCNT underflows.
Note that when H'0000 is written to DCNT, the corresponding DSTR bit is not cleared to 0
immediately; it is cleared to 0, and the down-counter is stopped, when underflow occurs following
the H'0000 write.
The timing in this case is shown in figure 11.70.
P
DCNT input clock
DCNT
Internal write signal
DSTR
TSR
N
H'0000
written
to DCNT
H'0000
H'0000
Port output
(one-shot pulse)
Figure 11.70 Halting of a Down-Counter by the CPU
Rev. 3.0, 09/04, page 418 of 1086