SH7058 Datasheet, PDF (763/1130 Pages) Renesas Technology Corp – Renesas SuperHTM RISC engine

Serial data
Instruction _{SDTRF Input}
Input/
output
1
0
1
H-UDI interrupt
request
SDTRF
(in SDSR)^*1
SDSR and
SDDR MUX^*2
Shift
enabled
SDDR access
state
Shift
disabled
Shift
enabled
SDSR SDDR
SDSR
SDDR
Shift
CPU
Shift
CPU
SDSR serial transfer
(monitoring)
Notes: 1. SDTRF flag (in SDSR): Indicates whether SDDR access by the CPU or serial transfer
data input/output to SDDR is possible.
1 SDDR is shift-disabled. SDDR access by the CPU is enabled.
2 SDDR is shift-enabled. Do not access SDDR until SDTRF = 0.
Conditions:
• SDTRF = 1
— When TRST = 0
— When the CPU writes 1
— In BYPASS mode
• SDTRF = 0
— End of SDDR shift access in serial transfer
2. SDSR/SDDR (Update-DR state) internal MUX switchover timing
• Switchover from SDSR to SDDR: On completion of serial transfer in which
SDTRF = 1 is output from TDO
• Switchover from SDDR to SDSR: On completion of serial transfer to SDDR
Figure 19.3 Data Input/Output Timing Chart (1)
Rev. 3.0, 09/04, page 722 of 1086