SH7058 Datasheet, PDF (1020/1130 Pages) Renesas Technology Corp – Renesas SuperHTM RISC engine

[Operating precautions]
1. Mode setup time during power-on reset by the RES pin depends on the combination of signals
to be input to the FWE and MD2 to MD0 pins. If a low-level signal is input to the RES pin
while this LSI operates by inputting a mode specified in table 27.3 to the FWE and MD2 to
MD0 pins, the mode setup time is defined by tMDS2. If a signal other than the combination of
signals specified in table 27.3 (undefined mode) is input to the FWE and MD2 to MD0 pins,
the mode setup time is defined by tMSD1. See section 27.6.2, Notes on Mode Pin Input.
2. The RES, NMI, and IRQ7–IRQ0 signals are asynchronous inputs, but when the setup times
shown here are provided, the signals are considered to have been changed at clock fall. If the
setup times are not provided, recognition is delayed until the next clock rise or fall.
3. The guaranteed operating range of power supply PV_CC1 in the MCU expanded modes is only
PV_CC1 = 3.3 V ±0.3 V. Do not use a voltage outside this range.
CK
MD2-0
t_RESS
V_IH = V_CC – 0.5 V
t_RESW
V_IL = 0.5 V
t_MD0
V_IH = V_CC – 0.5 V
V_IL = 0.5 V
V_OH
t_RESS
V_IH = V_CC – 0.5 V
V_IL = 0.5 V
Note:
pin is controlled by V_IL and V_IH shown above.
Figure 27.5 Reset Input Timing
Rev. 3.0, 09/04, page 979 of 1086