SH7058 Datasheet, PDF (602/1130 Pages) Renesas Technology Corp – Renesas SuperHTM RISC engine

Bit
Bit Name Initial Value R/W Description
0
IRR0
1
R/W Reset/Halt/Sleep Interrupt Flag
Indicates that the CAN interface has been reset or
halted and the HCAN is now in configuration
mode or in sleep mode.
An interrupt signal will be generated through this
bit to notify the change of the HCAN's state to the
host CPU if an MCR0 (software reset), MCR1
(halt), or MCR5 (sleep) request occurs. GSR can
be read after this bit is set to figure out which
state the HCAN is in.
Important: When a sleep mode request needs to
be made, halt mode should be used beforehand.
For details, see the MCR5 description.
0: Clearing condition: Writing 1
1: Transition to software reset mode, transition to
halt mode, or transition to sleep mode without
halt mode
Setting condition: When reset/halt processing is
completed after an MCR0 (software reset),
MCR1 (halt), or MCR5 (sleep) is requested
16.4.6 Interrupt Mask Register_n (IMR_n) (n = 0, 1)
The interrupt mask register (IMR) is a 16-bit register that masks output of corresponding interrupt
requests in the interrupt register (IRR). An interrupt request is masked if the corresponding bit is
set to 1. This register can be read or written to at any time. IMR directly controls the generation of
an interrupt request, but does not control the setting of the corresponding bit in IRR.
• IMR
Bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IMR IMR IMR IMR IMR IMR IMR IMR IMR IMR IMR IMR IMR IMR IMR IMR
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Initial Value: 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
R/W: R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Rev. 3.0, 09/04, page 561 of 1086