SH7058 Datasheet, PDF (617/1130 Pages) Renesas Technology Corp – Renesas SuperHTM RISC engine

16.5.6 Remote Frame Receive Pending Register n (RFPR1n, RFPR0n) (n = 0, 1)
RFPR1 and RFPR0 are 16-bit readable/conditionally-writable registers. RFPR is a register that
contains the remote request flags associated with the receive mailboxes. When a CAN remote
frame is successfully stored in a receive mailbox, the corresponding bit is set in RFPR. The
corresponding bit is cleared by writing 1. Writing 0 is ignored. There is a bit for all mailboxes.
However, the bit is only set if the mailbox is set by its MBC (mailbox configuration) to receive
remote frames. When an RFPR bit is set, IRR2 (remote frame request interrupt flag) is also set if
its MBIMR (mailbox interrupt mask register) is not set, and the interrupt signal is generated if
IMR2 is not set. These bits are only set by receiving remote frames and not by receiving data
frames.
If a data frame is overwritten/overrun with a remote frame or vice versa, UMSR, RXPR, and
RFPR will be set for the same mailbox. In this case the application needs to check the RTR bit
within the mailbox control field to understand the nature of the message on the mailbox.
Consequently when UMSR is set, both RXPR and RFPR should be checked and, if necessary,
cleared.
• RFPR1n (n = 0, 1)
Bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RFPR1[15:0]
Initial Value: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
R/W: R/ R/ R/ R/ R/ R/ R/ R/ R/ R/ R/ R/ R/ R/ R/ R/
WC1 WC1 WC1 WC1 WC1 WC1 WC1 WC1 WC1 WC1 WC1 WC1 WC1 WC1 WC1 WC1
Bit
Bit Name
15 to 0 RFPR1[15:0]
Initial Value
0
R/W
R/WC1
Description
Remote request wait flags for receive
mailboxes 31 to 16.
0: Clearing condition: Writing 1
1: Corresponding mailbox has received a
remote frame
Setting condition: Completion of remote
frame reception in corresponding mailbox
Rev. 3.0, 09/04, page 576 of 1086