SH7058 Datasheet, PDF (192/1130 Pages) Renesas Technology Corp – Renesas SuperHTM RISC engine

9.2.3 Wait Control Register (WCR)
Bit: 15
14
13
12
11
10
9
8
—
W32 W31 W30
—
W22 W21 W20
Initial value: 0
1
1
1
0
1
1
1
R/W: R
R/W R/W R/W
R
R/W R/W R/W
Bit: 7
6
5
4
3
2
1
0
—
W12 W11 W10
—
W02 W01 W00
Initial value: 0
1
1
1
0
1
1
1
R/W: R
R/W R/W R/W
R
R/W R/W R/W
WCR is a 16-bit readable/writable register that specifies the number of wait cycles for each CS
space.
WCR is initialized to H'7777 by a power-on reset and in hardware standby mode. It is not
initialized by a manual reset or in software standby mode.
• Bit 15—Reserved
• Bits 14–12—CS3 Space Wait Specification (W32, W31, W30): These bits specify the number
of waits for CS3 space access.
Bit 14:
W32
0
0
⋅⋅⋅
1
Bit 13:
W31
0
0
1
Bit 12:
W30
0
1
1
Description
No wait (external wait input disabled)
1 wait external wait input enabled
7 wait external wait input enabled
(Initial value)
• Bit 11—Reserved
• Bits 10–8—CS2 Space Wait Specification (W22, W21, W20): These bits specify the number
of waits for CS2 space access.
Bit 10:
W22
0
0
⋅⋅⋅
1
Bit 9:
W21
0
0
1
Bit 8:
W20
0
1
1
Description
No wait (external wait input disabled)
1 wait external wait input enabled
7 wait external wait input enabled
(Initial value)
Rev. 3.0, 09/04, page 151 of 1086