SH7058 Datasheet, PDF (312/1130 Pages) Renesas Technology Corp – Renesas SuperHTM RISC engine

• Bit 11—Input Capture/Compare-Match Flag 5B (IMF5B): Status flag that indicates GR5B
input capture or compare-match. The flag is not set in PWM mode.
Bit 11: IMF5B
0
1
Description
[Clearing condition]
(Initial value)
When IMF5B is read while set to 1, then 0 is written to IMF5B
[Setting conditions]
• When the TCNT5 value is transferred to GR5B by an input capture signal
while GR5B is functioning as an input capture register
• When TCNT5 = GR5B while GR5B is functioning as an output compare
register
• Bit 10—Input Capture/Compare-Match Flag 5A (IMF5A): Status flag that indicates GR5A
input capture or compare-match. The flag is not set in PWM mode.
Bit 10: IMF5A
0
1
Description
[Clearing condition]
(Initial value)
When IMF5A is read while set to 1, then 0 is written to IMF5A
[Setting conditions]
• When the TCNT5 value is transferred to GR5A by an input capture signal
while GR5A is functioning as an input capture register
• When TCNT5 = GR5A while GR5A is functioning as an output compare
register
• Bit 9—Overflow Flag 4 (OVF4): Status flag that indicates TCNT4 overflow.
Bit 9: OVF4
0
1
Description
[Clearing condition]
When OVF4 is read while set to 1, then 0 is written to OVF4
[Setting condition]
When the TCNT4 value overflows (from H'FFFF to H'0000)
(Initial value)
Rev. 3.0, 09/04, page 271 of 1086