SH7058 Datasheet, PDF (1037/1130 Pages) Renesas Technology Corp – Renesas SuperHTM RISC engine

27.3.12 AUD Timing
Table 27.17 shows AUD timing.
Table 27.17 AUD Timing
Conditions: V_CC = PLLV_CC = 3.3 V ±0.3 V, PV_CC1 = 5.0 V ±0.5 V/3.3 V ±0.3 V,
PV_CC2 = 5.0 V ±0.5 V, AV_CC = 5.0 V ±0.5 V, AV_ref = 4.5 V to AV_CC,
V_SS = PLLV_SS = AV_SS = 0 V, T_a = –40°C to 125°C.
When PV_CC1 = 3.3 V ±0.3 V, V_CC = PV_CC1.
When writing or erasing on-chip flash memory, T_a = –40°C to 85°C.
Item
Symbol Min
Max
Unit
AUDRST pulse width (Branch trace)
t_AUDRSTW
10
—
t_cyc
AUDRST pulse width (RAM monitor)
t_AUDRSTW
5
—
t_RMCYC
AUDMD setup time (Branch trace)
t
10
—
t
AUDMDS
cyc
AUDMD setup time (RAM monitor)
t
5
—
AUDMDS
t
RMCYC
Branch trace clock cycle
t
1
1
t
BTCYC
cyc
Branch trace clock duty
t_BTCKW
40
60
%
Branch trace data delay time
t_BTDD
—
40
ns
Branch trace data hold time
t
0
—
ns
BTDH
Branch trace SYNC delay time
t
—
40
ns
BTSD
Branch trace SYNC hold time
t
0
—
ns
BTSH
RAM monitor clock cycle
t_RMCYC
100
—
ns
RAM monitor clock low pulse width
t_RMCKW
45
—
ns
RAM monitor output data delay time
t_RMDD
7
t – _RMCYC 20 ns
RAM monitor output data hold time
t
5
—
ns
RMDHD
RAM monitor input data setup time
t
20
—
ns
RMDS
RAM monitor input data hold time
t_RMDH
5
—
ns
RAM monitor SYNC setup time
t_RMSS
20
—
ns
RAM monitor SYNC hold time
t_RMSH
5
—
ns
Load conditions: AUDCK (branch trace): CL = 30 pF: otherwise CL = 100 pF
AUDSYNC:
CL = 100 pF
AUDATA3 to AUDATA0: CL = 100 pF
Figures
Figure 27.25
Figure 27.26
Figure 27.27
Rev. 3.0, 09/04, page 996 of 1086