SH7058 Datasheet, PDF (48/1130 Pages) Renesas Technology Corp – Renesas SuperHTM RISC engine

Table 1.1 SH7058 Features (cont)
Item
RAM
Features
• 48 kB SRAM
1.2 Block Diagram
RES
HSTBY
FWE
MD2
MD1
MD0
NMI
WDTOVF
CK
EXTAL
XTAL
PLLV_CC
PLLV_SS
PLLCAP
Vcc (×8)
PVcc1 (×4)
PVcc2 (×6)
VCL(×3)
Vss (×21)
AVref (×2)
AVcc (×2)
AVss (×2)
AN31–0
AUDRST
AUDMD
AUDATA3–0
AUDCK
AUDSYNC
TMS
TRST
TDI
TDO
TCK
PD0/TIO1A
PD1/TIO1B
PD2/TIO1C
PD3/TIO1D
PD4/TIO1E
PD5/TIO1F
PD6/TIO1G
PD7/TIO1H
PD8/PULS0
PD9/PULS1
PD10/PULS2
PD11/PULS3
PD12/PULS4
PD13/PULS6/HTxD0/HTxD1
PL0/TI10
PL1/TIO11A/IRQ6
PL2/TIO11B/IRQ7
PL3/TCLKB
PL4/ADTRG0
PL5/ADTRG1
PL6/ADEND
PL7/SCK2
PL8/SCK3
PL9/SCK4/IRQ5
PL10/HTxD0/HTxD1/HTxD0 & HTxD1
PL11/HRxD0/HRxD1/HRxD0 & HRxD1
PL12/IRQ4
PL13/IRQOUT
Port/control signals
Port/address signals
ROM (flash)
1 MB
RAM
48 kB
Clock pulse
generator
CPU
FPU
Multiplier
Interrupt
controller
DMAC
(4 channels)
BSC
SCI (5 channels)
HCAN II (2 channels)
ATU-II
CMT (2 channels)
AUD
H-UDI
A/D
converter
WDT
Port
Port
: Peripheral address bus (9 bits)
: Peripheral data bus (16 bits)
: Internal address bus (32 bits)
: Internal upper data bus (16 bits)
: Internal lower data bus (16 bits)
PH15/D15
PH14/D14
PH13/D13
PH12/D12
PH11/D11
PH10/D10
PH9/D9
PH8/D8
PH7/D7
PH6/D6
PH5/D5
PH4/D4
PH3/D3
PH2/D2
PH1/D1
PH0/D0
PA0/TI0A
PA1/TI0B
PA2/TI0C
PA3/TI0D
PA4/TIO3A
PA5/TIO3B
PA6/TIO3C
PA7/TIO3D
PA8/TIO4A/ADTO0A
PA9/TIO4B/ADTO0B
PA10/TIO4C/ADTO1A
PA11/TIO4D/ADTO1B
PA12/TIO5A
PA13/TIO5B
PA14/TxD0
PA15/RxD0
PB0/TO6A
PB1/TO6B
PB2/TO6C
PB3/TO6D
PB4/TO7A/TO8A
PB5/TO7B/TO8B
PB6/TO7C/TO8C
PB7/TO7D/TO8D
PB8/TxD3/TO8E
PB9/RxD3/TO8F
PB10/TxD4/HTxD0/TO8G
PB11/RxD4/HRxD0/TO8H
PB12/TCLKA/UBCTRG
PB13/SCK0
PB14/SCK1/TCLKB/TI10
PB15/PULS5/SCK2
PC0/TxD1
PC1/RxD1
PC2/TxD2
PC3/RxD2
PC4/IRQ0
PG0/PULS7/HRxD0/HRxD1
PG1/IRQ1
PG2/IRQ2/ADEND
PG3/IRQ3/ADTRG0
Figure 1.1 Block Diagram
Rev. 3.0, 09/04, page 7 of 1086