SH7058 Datasheet, PDF (162/1130 Pages) Renesas Technology Corp – Renesas SuperHTM RISC engine

7.4.2 Stack after Interrupt Exception Processing
Figure 7.3 shows the stack after interrupt exception processing.
Address
4n–8
4n–4
4n
PC*¹
SR
32 bits
32 bits
SP*²
Notes: 1. PC: Start address of the next instruction (return destination instruction)
after the executing instruction
2. Always be certain that SP is a multiple of 4
Figure 7.3 Stack after Interrupt Exception Processing
Rev. 3.0, 09/04, page 121 of 1086