SH7058 Datasheet, PDF (211/1130 Pages) Renesas Technology Corp – Renesas SuperHTM RISC engine

10.2.4 DMA Channel Control Registers 0–3 (CHCR0–CHCR3)
Bit: 31
30
29
28
27
26
—
—
—
DI
—
—
Initial value: 0
0
0
0
0
0
R/W: R
R
R
R/W*²
R
R
25
24
—
RO
0
0
R
R/W*²
Bit: 23
22
21
20
19
18
17
16
—
—
—
RS4 RS3 RS2 RS1 RS0
Initial value: 0
0
0
0
0
0
0
0
R/W: R
R
R
R/W
R/W
R/W R/W*¹ R/W
Bit: 15
—
Initial value: 0
R/W: R
14
13
12
11
—
SM1 SM0
—
0
0
0
0
R
R/W R/W
R
10
9
8
—
DM1 DM0
0
0
0
R
R/W R/W
Bit: 7
6
5
4
3
2
1
0
—
—
TS1 TS0
TM
IE
TE
DE
Initial value: 0
0
0
0
0
0
0
0
R/W: R
R
R/W
R/W
R/W
R/W R/(W)*¹ R/W
Notes: 1. TE bit: Allows only a 0 write after reading 1.
2. The DI and RO bits may be absent, depending on the channel.
DMA channel control registers 0–3 (CHCR0–CHCR3) are 32-bit readable/writable registers that
designate the operation and transmission of each channel. CHCR register bits are initialized to
H'00000000 by a power-on reset and in standby mode.
Rev. 3.0, 09/04, page 170 of 1086