SH7058 Datasheet, PDF(240/1130 Page) Renesas Technology Corp – Renesas SuperHTM RISC engine

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SH7058 Datasheet, PDF (240/1130 Pages) Renesas Technology Corp – Renesas SuperHTM RISC engine

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Section 11 Advanced Timer Unit-II (ATU-II)

11.1 Overview

The SH7058 has an on-chip advanced timer unit-II (ATU-II) with one 32-bit timer channel and

eleven 16-bit timer channels.

11.1.1 Features

ATU-II features are summarized below.

â¢ Capability to process up to 65 pulse inputs and outputs

â¢ Prescaler

ï£§ Input clock to channels 0 and 10 scaled in 1 stage, input clock to channels 1 to 8 and 11

scaled in 2 stages

ï£§ 1/1 to 1/32 clock scaling possible in initial stage for channels 0 to 8, 10, and 11

ï£§ 1/1, 1/2, 1/4, 1/8, 1/16, or 1/32 scaling possible in second stage for channels 1 to 8 and 11

ï£§ External clock TCLKA, TCLKB selection also possible for channels 1 to 5 and 11

ï£§ TI10, TI10 multiplication (compensation) selection possible for channels 1 to 5: AGCK,

AGCKM

â¢ Channel 0 has four 32-bit input capture lines, allowing the following operations:

ï£§ Rising-edge, falling-edge, or both-edge detection selectable

ï£§ DMAC can be activated at capture timing

ï£§ Channel 10 compare-match signal can be captured as a trigger

ï£§ Interval interrupt generation function generates three interval interrupts as selected. CPU

interruption or A/D converter (AD0, 1, 2) activation possible

ï£§ Capture interrupt and counter overflow interrupt can be generated

â¢ Channel 1 has one 16-bit output compare register, eight general registers, and one dedicated

input capture register. The output compare register can also be selected for one-shot pulse

offset in combination with the channel 8 down-counter.

ï£§ General registers (GR1AâH) can be used as input capture or output compare registers

ï£§ Waveform output by means of compare-match: Selection of 0 output, 1 output, or toggle

output

ï£§ Input capture function: Rising-edge, falling-edge, or both-edge detection

ï£§ Channel 0 input signal (TI0A) can be captured as trigger

ï£§ Provision for forcible cutoff of channel 8 down-counters (DCNT8AâH)

ï£§ Compare-match interrupts/capture interrupts and counter overflow interrupts can be

generated

Rev. 3.0, 09/04, page 199 of 1086

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