SH7058 Datasheet, PDF (193/1130 Pages) Renesas Technology Corp – Renesas SuperHTM RISC engine

• Bit 7—Reserved
• Bits 6–4—CS1 Space Wait Specification (W12, W11, W10): These bits specify the number of
waits for CS1 space access.
Bit 6:
W12
0
0
⋅⋅⋅
1
Bit 5:
W11
0
0
1
Bit 4:
W10
0
1
1
Description
No wait (external wait input disabled)
1 wait external wait input enabled
7 wait external wait input enabled
(Initial value)
• Bit 3—Reserved
• Bits 2–0—CS0 Space Wait Specification (W02, W01, W00): These bits specify the number of
waits for CS0 space access.
Bit 2:
W02
0
0
⋅⋅⋅
1
Bit 1:
W01
0
0
1
Bit 0:
W00
0
1
1
Description
No wait (external wait input disabled)
1 wait external wait input enabled
7 wait external wait input enabled
(Initial value)
9.2.4 RAM Emulation Register (RAMER)
Bit: 15
14
13
12
11
10
9
8
—
—
—
—
—
—
—
—
Initial value: 0
0
0
0
0
0
0
0
R/W: R
R
R
R
R
R
R
R
Bit: 7
6
5
4
3
2
1
0
—
—
—
— RAMS RAM2 RAM1 RAM0
Initial value: 0
0
0
0
0
0
0
0
R/W: R
R
R
R
R/W R/W R/W R/W
The RAM emulation register (RAMER) is a 16-bit readable/writable register that selects the RAM
area to be used when emulating realtime programming of flash memory.
RAMER is initialized to H'0000 by a power-on reset and in hardware standby mode. It is not
initialized by a manual reset or in software standby mode.
Rev. 3.0, 09/04, page 152 of 1086