SH7058 Datasheet, PDF (134/1130 Pages) Renesas Technology Corp – Renesas SuperHTM RISC engine

6.3.2 Address Error Exception Processing
When an address error occurs, the bus cycle in which the address error occurred ends. When the
executing instruction then finishes, address error exception processing starts up. The CPU operates
as follows:
1. The status register (SR) is saved to the stack.
2. The program counter (PC) is saved to the stack. The PC value saved is the start address of the
instruction to be executed after the last executed instruction.
3. The exception service routine start address is fetched from the exception processing vector
table that corresponds to the address error that occurred and the program starts executing from
that address. The jump that occurs is not a delayed branch.
6.4 Interrupts
6.4.1 Interrupt Sources
Table 6.7 shows the sources that start up interrupt exception processing. These are divided into
NMI, user breaks, H-UDI, IRQ, and on-chip peripheral modules.
Table 6.7 Interrupt Sources
Type
NMI
User break
H-UDI
IRQ
On-chip peripheral module
Request Source
NMI pin (external input)
User break controller
High-performance user debug interface
IRQ0–IRQ7 (external input)
Direct memory access controller (DMAC)
Advanced timer unit (ATU-II)
Compare match timer (CMT)
A/D converter
Serial communication interface (SCI)
Watchdog timer (WDT)
Controller area network (HCAN)
Number of
Sources
1
1
1
8
4
75
2
3
20
1
8
Each interrupt source is allocated a different vector number and vector table offset. See table 7.3,
Interrupt Exception Processing Vectors and Priorities, in section 7, Interrupt Controller (INTC),
for more information on vector numbers and vector table address offsets.
Rev. 3.0, 09/04, page 93 of 1086