SH7058 Datasheet, PDF (410/1130 Pages) Renesas Technology Corp – Renesas SuperHTM RISC engine

Channel 1 and 2 GR and OCR registers can send a trigger/terminate signal to channel 8 when a
compare-match occurs. In this case, settings should be made in the trigger mode register
(TRGMDR), timer connection register (TCNR), and one-shot pulse terminate register (OTR).
An example of compare-match operation is shown in figure 11.15.
In the example in figure 11.15, channel 1 is activated, and external output is performed with toggle
output specified for GR1A, 1 output for GR1B, and 0 output for GR1C.
P
TCNT1
Clock
TCNT1 003C
003D
003E
003F
0040
007E
GR1A–1C
003E
TIO1A
007F
0080
0081
0082
0083
0084
0085
0081
TIO1B
TIO1C
TSR1
IMF1A–1D
Channel 8
start/terminate
trigger signal
Cleared by software
Cleared by software
Figure 11.15 Compare-Match Operation
11.3.4 Input Capture Function
If input capture registers (ICR0A to ICR0D) and general registers (GR1A to GR1H, GR2A to
GR2H, GR3A to GR3D, GR4A to GR4D, GR5A to GR5D, GR11A, GR11B) in channels 1 to 5
and 11 are designated for input capture operation in the timer I/O control registers (TIOR0 to
TIOR5, TIOR11), input capture is performed when an edge is input at the corresponding external
pins (TI0A to TI0D, TIO1A to TIO1H, TIO2A to TIO2H, TIO3A to TIO3D, TIO4A to TIO4D,
TIO5A to TIO5D).
A free-running counter (TCNT) starts counting up when a setting is made in the timer start register
(TSTR). When an edge is input at an external pin corresponding to ICR or GR, the corresponding
timer status register (TSR) bit is set and the TCNT value is transferred to ICR or GR. Rising-edge,
falling-edge, or both-edge detection can be selected. By making the appropriate setting in the
interrupt enable register (TIER), an interrupt request can be sent to the CPU.
Rev. 3.0, 09/04, page 369 of 1086