SH7058 Datasheet, PDF (731/1130 Pages) Renesas Technology Corp – Renesas SuperHTM RISC engine

Software Operation
1. A compare match flag is cleared.
2. The value in the A/D general register (ADGR) is changed.
3. A/D select (ADSEL) in the A/D trigger control register (ADTCR) is changed.
After Multi-trigger A/D conversion is Over
4. The multi-trigger A/D conversion end flag is cleared.
5. The conversion result is read out.
(B)
Hardware Operation
1. A compare match occurs, setting the status flag to the corresponding source.
2. An interrupt is generated if the A/D duty enable bit (ADDE) in the A/D trigger interrupt enable
register (ADTIER) is set.
3. The level of the external output pin is changed.
Software Operation
1. The duty compare match flag is cleared.
(C)
Hardware Operation
1. A compare match occurs, setting the status flag to the corresponding source.
2. An interrupt is generated if the A/D cycle enable bit (ADCYLR) in the A/D trigger interrupt
enable register (ADTIER) is set.
3. The level of the external output pin is changed.
Software Operation
1. The cycle compare match flag is cleared.
2. The values in the A/D duty register (ADDR) and the A/D cycle register (ADCYLR) are
changed.
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