SH7058 Datasheet, PDF (739/1130 Pages) Renesas Technology Corp – Renesas SuperHTM RISC engine

Table 19.3 shows the kinds of serial transfer possible with each register.
Table 19.3 H-UDI Register Serial Transfer
Register
SDIR
SDSR
SDDRH
SDDRL
SDBPR
SDBSR
SDIDR
Serial Input
Possible
Impossible
Possible
Possible
Possible
Possible
Impossible
Serial Output
Possible
Possible
Possible
Possible
Possible
Possible
Possible
19.2 External Signals
19.2.1 Test Clock (TCK)
The test clock pin (TCK) provides an independent clock supply to the H-UDI. As the clock input
to TCK is supplied directly to the H-UDI, a clock waveform with a duty cycle close to 50% should
be input (for details, see section 27, Electrical Characteristics). If no signal is input, TCK is fixed
at 1 by internal pull-up.
19.2.2 Test Mode Select (TMS)
The test mode select pin (TMS) is sampled at the rise of TCK. TMS controls the internal state of
the TAP controller. If no signal is input, TMS is fixed at 1 by internal pull-up.
19.2.3 Test Data Input (TDI)
The test data input pin (TDI) performs serial input of instructions and data for H-UDI registers.
TDI is sampled at the rise of TCK. If no signal is input, TDI is fixed at 1 by internal pull-up.
19.2.4 Test Data Output (TDO)
The test data output pin (TDO) performs serial output of instructions and data from H-UDI
registers. Transfer is performed in synchronization with TCK. If there is no output, TDO goes to
the high-impedance state.
Rev. 3.0, 09/04, page 698 of 1086