SH7058 Datasheet, PDF (435/1130 Pages) Renesas Technology Corp – Renesas SuperHTM RISC engine

Clearing by DMAC: The interrupt status flag (ICF0A to ICF0D, CMF6A to CMF6D, CMF7A to
CMF7D) is cleared automatically during data transfer when the DMAC is activated by input
capture or compare-match.
The procedure and timing in this case are shown in figure 11.43.
CK
Start
Clear request signal
from DMAC
Activate DMAC
Interrupt status
flag clear signal
Interrupt status flag
Interrupt status
ICF0B, CMF6
flag cleared during
data transfer
Interrupt request
signal
Figure 11.43 Procedure and Timing for Clearing by DMAC
Rev. 3.0, 09/04, page 394 of 1086