SH7058 Datasheet, PDF (860/1130 Pages) Renesas Technology Corp – Renesas SuperHTM RISC engine

22.8.1 Register Configuration
The port G register configuration is shown in table 22.13.
Table 22.13 Register Configuration
Name
Abbreviation R/W Initial Value Address
Access Size
Port G data register PGDR
R/W H'0000
H'FFFFF764 8, 16
Note: Register access with an internal clock multiplication ratio of 4 requires four or five internal
clock (φ) cycles.
22.8.2 Port G Data Register (PGDR)
Bit: 15
14
13
12
11
10
9
8
—
—
—
—
—
—
—
—
Initial value: 0
0
0
0
0
0
0
0
R/W: R
R
R
R
R
R
R
R
Bit: 7
6
5
4
3
2
1
0
—
—
—
—
PG3 PG2 PG1 PG0
DR
DR
DR
DR
Initial value: 0
0
0
0
0
0
0
0
R/W: R
R
R
R
R/W R/W R/W R/W
The port G data register (PGDR) is a 16-bit readable/writable register that stores port G data.
Bits PG3DR to PG0DR correspond to pins PG3/IRQ3/ADTRG0 to
PG0/PULS7/HRxD0/HRxD1.
When a pin functions as a general output, if a value is written to PGDR, that value is output
directly from the pin, and if PGDR is read, the register value is returned directly regardless of
the pin state.
When a pin functions as a general input, if PGDR is read, the pin state, not the register value, is
returned directly. If a value is written to PGDR, although that value is written into PGDR, it
does not affect the pin state. Table 22.14 summarizes port G data register read/write operations.
PGDR is initialized to H'0000 by a power-on reset (excluding a WDT power-on reset), and in
hardware standby mode. It is not initialized in software standby mode or sleep mode.
• Bits 15 to 4—Reserved: These its are always read as 0. The write value should always be 0.
Rev. 3.0, 09/04, page 819 of 1086