SH7058 Datasheet, PDF (887/1130 Pages) Renesas Technology Corp – Renesas SuperHTM RISC engine

23.4.2 Programming/Erasing Interface Registers
The programming/erasing interface registers are as described below. They are all 8-bit registers
that can be accessed in bytes. Except for the FLER bit in FCCS and FMATS, these registers are
initialized at a power-on reset, in hardware standby mode, or in software standby mode. The
FLER bit or FMATS is not initialized in software standby mode.
(1) Flash Code Control and Status Register (FCCS)
FCCS is configured by bits which request the monitor of the FWE pin state and error
occurrence during programming or erasing flash memory and the download of the on-chip
program.
Bit :
7
6
5
4
3
2
1
0
FWE
—
—
FLER
—
—
—
SCO
Initial value : 1/0
0
0
0
0
0
0
0
R/W :
R
R
R
R
R
R
R
(R)W
• Bit 7—Flash Programming Enable (FWE): Monitors the level which is input to the FWE pin
that performs hardware protection of the flash memory programming or erasing. The initial
value is 0 or 1 according to the FWE pin state.
Bit 7
FWE
Description
0
When the FWE pin goes low (in hardware protection state)
1
When the FWE pin goes high
• Bits 6 and 5—Reserved: These bits are always read as 0. The write value should always be 0.
• Bit 4—Flash Memory Error (FLER): Indicates an error occurs during programming and
erasing flash memory.
When FLER is set to 1, flash memory enters the error protection state.
This bit is initialized at a power-on reset or in hardware standby mode.
When FLER is set to 1, high voltage is applied to the internal flash memory. To reduce the
damage to flash memory, the reset signal must be released after the reset period of 100 µs which is
longer than normal.
Rev. 3.0, 09/04, page 846 of 1086