SH7058 Datasheet, PDF (173/1130 Pages) Renesas Technology Corp – Renesas SuperHTM RISC engine

8.2.4 User Break Control Register (UBCR)
Bit: 15
14
13
12
11
10
9
8
—
—
—
—
—
—
—
—
Initial value: 0
0
0
0
0
0
0
0
R/W: R
R
R
R
R
R
R
R
Bit: 7
6
5
4
3
2
1
0
—
—
—
—
—
CKS1 CKS0 UBID
Initial value: 0
0
0
0
0
0
0
0
R/W: R
R
R
R
R
R/W R/W R/W
The user break control register (UBCR) is a 16-bit readable/writable register that (1) enables or
disables user break interrupts and (2) sets the pulse width of the UBCTRG signal output in the
event of a break condition match.
UBCR is initialized to H'0000 by a power-on reset and in module standby mode. It is not
initialized in software standby mode.
• Bits 15 to 3—Reserved: These bits are always read as 0. The write value should always be 0.
• Bits 2 and 1—Clock Select 1 and 0 (CKS1, CKS0): These bits specify the pulse width of the
UBCTRG signal output in the event of a condition match.
Bit 2: CKS1
Bit 1: CKS0 Description
0
0
When the internal clock is four times an input clock, UBCTRG
pulse width is φ/2
When the internal clock is eight times an input clock,
UBCTRG pulse width is φ/4
(Initial value)
1
UBCTRG pulse width is φ/4
1
0
UBCTRG pulse width is φ/8
1
UBCTRG pulse width is φ/16
Notes: φ: Internal clock
See section 8.5.7, Internal Clock (φ) Multiplication Ratio and UBCTRG Pulse Width.
• Bit 0—User Break Disable (UBID): Enables or disables user break interrupt request generation
in the event of a user break condition match.
Bit 0: UBID
0
1
Description
User break interrupt request is enabled
User break interrupt request is disabled
(Initial value)
Rev. 3.0, 09/04, page 132 of 1086