SH7058 Datasheet, PDF (314/1130 Pages) Renesas Technology Corp – Renesas SuperHTM RISC engine

• Bit 5—Input Capture/Compare-Match Flag 4A (IMF4A): Status flag that indicates GR4A
input capture or compare-match. The flag is not set in PWM mode.
Bit 5: IMF4A
0
1
Description
[Clearing condition]
(Initial value)
When IMF4A is read while set to 1, then 0 is written to IMF4A
[Setting conditions]
• When the TCNT4 value is transferred to GR4A by an input capture signal
while GR4A is functioning as an input capture register
• When TCNT4 = GR4A while GR4A is functioning as an output compare
register
• Bit 4—Overflow Flag 3 (OVF3): Status flag that indicates TCNT3 input capture or compare-
match.
Bit 4: OVF3
0
1
Description
[Clearing condition]
When OVF3 is read while set to 1, then 0 is written to OVF3
[Setting condition]
When the TCNT3 value overflows (from H'FFFF to H'0000)
(Initial value)
• Bit 3—Input Capture/Compare-Match Flag 3D (IMF3D): Status flag that indicates GR5D
input capture or compare-match.
Bit 3: IMF3D
0
1
Description
[Clearing condition]
(Initial value)
When IMF3D is read while set to 1, then 0 is written to IMF3D
[Setting conditions]
• When the TCNT3 value is transferred to GR3D by an input capture signal
while GR3D is functioning as an input capture register. However, IMF3D
is not set by input capture with a channel 9 compare match as the trigger
• When TCNT3 = GR3D while GR3D is functioning as an output compare
register
• When TCNT3 = GR3D while GR3D is functioning as a synchronous
register in PWM mode
Rev. 3.0, 09/04, page 273 of 1086