SH7058 Datasheet, PDF (639/1130 Pages) Renesas Technology Corp – Renesas SuperHTM RISC engine

16.7.2 HCAN Settings
• Reset Sequence
The following sequence is an example to set the HCAN after a software or hardware reset. After a
reset, all the registers are initialized, therefore, the HCAN needs to be set before joining the CAN
bus activity. Please read the notes carefully.
Reset Sequence
Configuration Mode
Power-on/software reset^*1
Clear MCR[0]
Transmission mode
GSR3 = 0?
No
Clear all mailboxes^*2
Yes
(MSG-control, data, timestamp,
LAFM)
Clear IRR[0]
Clear required IMR bits
Set LAFM
Mailbox setting
(STD-ID, EXT-ID, DLC, RTR,
IDE, MBC, MBIMR, ATX,
NMC, LAFM, message data)
HCAN-II is in normal mode
Set TXPR to start transmission
or stay idle to receive
Normal Mode
Detect 11 recessive bits and
join the CAN bus activity
Set bit configuration register
(BCR)
Receive^*3
Transmit^*3
Notes: 1.
2.
3.
A software reset can be performed at any time by setting MCR [0] = 1.
Mailboxes are comprised of RAMs, therefore, initialize all the mailboxes first
even if some of them are not used.
If TXPR is not set, the HCAN-II starts the message reception. If TXPR is set,
the HCAN-II starts transmission of the message and is arbitrated by the CAN bus.
If an arbitration loss occurs, reception starts.
Figure 16.7 Reset Sequence
Rev. 3.0, 09/04, page 598 of 1086