SH7058 Datasheet, PDF (591/1130 Pages) Renesas Technology Corp – Renesas SuperHTM RISC engine

Bit
Bit Name Initial Value R/W Description
3
GSR3
1
R
Reset Status
Indicates whether the CAN interface is in the reset
state (configuration mode) or not.
0: Normal operating state
Setting condition: After an HCAN internal reset
1: Reset state (configuration mode)
2
GSR2
1
R
Message Transmission In Progress Flag
Indicates to the host CPU if the HCAN is
processing transmission requests or if a
transmission is completed. This bit is an ORed
signal of all the TXPR bits. Note that the IRR8
(slot empty) is an ORed signal of all the
TXACK/ABACK bits.
0: Transmission in progress
1: There is no message requested for
transmission
1
GSR1
0
R
Transmit/Receive Warning Flag
Indicates an error warning.
0: Reset condition: When TEC < 96, REC < 96, or
TEC ≥ 256
1: When 96 ≤ TEC < 256 or 96 ≤ REC
0
GSR0
0
R
Bus Off Flag
Indicates that the HCAN is in the bus off state.
0: Reset condition: Recovery from bus off state
1: When TEC ≥ 256 (bus off state)
16.4.4 HCAN-II_Bit timing Configuration Register n
(HCAN-II_BCR0_n, HCAN-II_BCR1_n) (n = 0, 1)
The bit configuration registers (BCR0 and BCR1) are 16-bit readable/writable registers that set
CAN bit timing parameters and the baud rate prescaler for the CAN interface.
For the following description the following definition is used:
Timequanta = ^BRP
f_clk
Where: BRP (baud rate predivider) is stored in BCR0 and fclk is Pφ (peripheral clock).
Rev. 3.0, 09/04, page 550 of 1086