SH7058 Datasheet, PDF (847/1130 Pages) Renesas Technology Corp – Renesas SuperHTM RISC engine

22.3 Port B
Port B is an input/output port with the 16 pins shown in figure 21.2.
Port B
PB15 (I/O) /PULS5 (output) /SCK2 (I/O)
PB14 (I/O) /SCK1 (I/O) /TCLKB (input) /TI10 (input)
PB13 (I/O) /SCK0 (I/O)
PB12 (I/O) /TCLKA (input) /
(output)
PB11 (I/O) /RxD4 (input) /HRxD0 (input) /TO8H (output)
PB10 (I/O) /TxD4 (output) /HTxD0 (output) /TO8G (output)
PB9 (I/O) /RxD3 (input) /TO8F (output)
PB8 (I/O) /TxD3 (output) /TO8E (output)
PB7 (I/O) /TO7D (output) /TO8D (output)
PB6 (I/O) /TO7C (output) /TO8C (output)
PB5 (I/O) /TO7B (output) /TO8B (output)
PB4 (I/O) /TO7A (output) /TO8A (output)
PB3 (I/O) /TO6D (output)
PB2 (I/O) /TO6C (output)
PB1 (I/O) /TO6B (output)
PB0 (I/O) /TO6A (output)
Figure 22.2 Port B
22.3.1 Register Configuration
The port B register configuration is shown in table 22.3.
Table 22.3 Register Configuration
Name
Abbreviation R/W Initial Value Address
Access Size
Port B data register PBDR
R/W H'0000
H'FFFFF738 8, 16
Port B port register PBPR
R
Port B pin
H'FFFFF782 8, 16
values
Note: Register access with an internal clock multiplication ratio of 4 requires four or five internal
clock (φ) cycles.
Rev. 3.0, 09/04, page 806 of 1086