SH7058 Datasheet, PDF (179/1130 Pages) Renesas Technology Corp – Renesas SuperHTM RISC engine

8.5 Usage Notes
8.5.1 Simultaneous Fetching of Two Instructions
Two instructions may be simultaneously fetched from on-chip memory. If a break condition is set
on the second of these two instructions but the contents of the UBC break condition registers are
changed so as to alter the break condition immediately after the first of the two instructions is
fetched, a user break interrupt will still occur when the second instruction is fetched.
8.5.2 Instruction Fetches at Branches
When a conditional branch instruction or TRAPA instruction causes a branch, the order of
instruction fetching and execution is as follows:
1. When branching with a conditional branch instruction: BT and BF instructions
When branching with a TRAPA instruction:
TRAPA instruction
Instruction fetch order:
Branch instruction fetch → next instruction overrun fetch →
overrun fetch of instruction after next → branch destination
instruction fetch
Instruction execution order: Branch instruction execution → branch destination instruction
execution
2. When branching with a delayed conditional branch instruction: BT/S and BF/S instructions
Instruction fetch order:
Branch instruction fetch → next instruction fetch (delay slot) →
overrun fetch of instruction after next → branch destination
instruction fetch
Instruction execution order: Branch instruction execution → delay slot instruction execution
→ branch destination instruction execution
Thus, when a conditional branch instruction or TRAPA instruction causes a branch, the branch
destination instruction will be fetched after an overrun fetch of the next instruction or the
instruction after next. However, as the instruction that is the object of the break does not break
until fetching and execution of the instruction have been confirmed, the overrun fetches described
above do not become objects of a break.
If data accesses are also included as break conditions in addition to instruction fetch breaks, a
break will occur because the instruction overrun fetch is also regarded as satisfying the data break
condition.
Rev. 3.0, 09/04, page 138 of 1086