SH7058 Datasheet, PDF (284/1130 Pages) Renesas Technology Corp – Renesas SuperHTM RISC engine

Bit 1: EGSELx1
0
1
x = A, C, or E
Bit 0: EGSELx0
0
1
0
1
Description
Count disabled
Rising edges counted
Falling edges counted
Both rising and falling edges counted
(Initial value)
Timer Control Register 11 (TCR11)
Bit: 7
—
Initial value: 0
R/W: R
6
5
4
—
CKEG1 CKEG0
0
0
0
R
R/W
R/W
3
2
1
0
— CKSELA2 CKSELA1 CKSELA0
0
0
0
0
R
R/W
R/W
R/W
• Bits 7, 6, and 3—Reserved: These bits are always read as 0. The write value should always be
0.
• Bits 5 and 4—Edge Select: These bits select the event counter counted edge(s).
Bit 5: CKEG1
0
1
Bit 4: CKEG0
0
1
0
1
Description
Rising edges counted
Falling edges counted
Both rising and falling edges counted
Count disabled
(Initial value)
• Bits 2 to 0—Clock Select A2 to A0 (CKSELA2 to CKSELA0): These bits select clock φ",
scaled from the internal clock source, from φ', φ'/2, φ'/4, φ'/8, φ'/16, and φ'/32.
Bit 2:
CKSELA2
0
1
Bit 1:
CKSELA1
0
1
0
1
Bit 0:
CKSELA0
0
1
0
1
0
1
0
1
Description
Internal clock φ": counting on φ'
(Initial value)
Internal clock φ": counting on φ'/2
Internal clock φ": counting on φ'/4
Internal clock φ": counting on φ'/8
Internal clock φ": counting on φ'/16
Internal clock φ": counting on φ'/32
External clock: counting on TCLKA pin input
External clock: counting on TCLKB pin input
Rev. 3.0, 09/04, page 243 of 1086