SH7058 Datasheet, PDF (628/1130 Pages) Renesas Technology Corp – Renesas SuperHTM RISC engine

Bit
Bit Name Initial Value R/W Description
4
TSR4
0
R
Cycle Counter Overflow Flag
Indicates that the cycle counter has reached its
maximum value and is reset to H'0. Setting CMAX
= 0 makes the cycle counter be disabled and
TSR4 be always cleared to 0.
0: Cycle counter has not overflow
Clearing condition: Writing 1 to IRR10 (cycle
counter overflow interrupt)
1: Cycle counter has overflow
Setting condition: When the cycle counter value
changes from the maximum value (CMAX) to
H'0
3
TSR3
0
R
Timer Compare Match Flag 2
Indicates that a compare-match condition
occurred to the timer compare match register 2
(TCMR2). When the value set in TCMR2 matches
the timer value (TCMR2 = TCNTR), this bit is set.
This bit is not set if the TCMR2 value is H'0000.
Also, this bit is read-only and is cleared when
IRR11 (timer compare match interrupt 2) is
cleared.
0: Timer compare match has not occurred to
TCMR2
Clearing condition: Writing 1 to IRR11 (timer
compare match interrupt 2)
1: Timer compare match has occurred to TCMR2
Setting condition: TCMR2 matches the timer
value (TCMR2 = TCNTR)
Rev. 3.0, 09/04, page 587 of 1086