SH7058 Datasheet, PDF (870/1130 Pages) Renesas Technology Corp – Renesas SuperHTM RISC engine

22.12.2 Port L Data Register (PLDR)
Bit: 15
—
Initial value: 0
R/W: R
14
13
12
11
10
9
8
—
PL13 PL12 PL11 PL10 PL9
PL8
DR
DR
DR
DR
DR
DR
0
0
0
0
0
0
0
R
R/W R/W R/W R/W R/W R/W
Bit: 7
6
5
4
3
2
1
0
PL7
PL6
PL5
PL4
PL3
PL2
PL1
PL0
DR
DR
DR
DR
DR
DR
DR
DR
Initial value: 0
0
0
0
0
0
0
0
R/W: R/W R/W R/W R/W R/W R/W R/W R/W
The port L data register (PLDR) is a 16-bit readable/writable register that stores port L data. Bits
PL13DR to PL0DR correspond to pins PL13/IRQOUT to PL0/TI10.
When a pin functions as a general output, if a value is written to PLDR, that value is output
directly from the pin, and if PLDR is read, the register value is returned directly regardless of the
pin state.
When a pin functions as a general input, if PLDR is read, the pin state, not the register value, is
returned directly. If a value is written to PLDR, although that value is written into PLDR, it does
not affect the pin state. Table 22.22 summarizes port L data register read/write operations.
PLDR is initialized to H'0000 by a power-on reset (excluding a WDT power-on reset), and in
hardware standby mode. It is not initialized in software standby mode or sleep mode.
• Bits 15 and 14—Reserved: These bits are always read as 0. The write value should always be
0.
Rev. 3.0, 09/04, page 829 of 1086