SH7058 Datasheet, PDF (698/1130 Pages) Renesas Technology Corp – Renesas SuperHTM RISC engine

• Bit 0—A/D Data Select 1A (ADSEL1A): Selects the register to which the result of multi-
trigger A/D conversion is transferred.
This bit is inverted when the ADDR register is updated by the multi-trigger A/D conversion.
Switching settings during the multi-trigger A/D conversion operation should be carried out
when TADF1A (ADTSR1 register) is set to 1.
Bit 0:
ADSEL1A
0
1
Description
Conversion result is transferred into ADDR20
Conversion result is transferred into ADDR21
(Initial value)
• Bit 0—A/D Data Select 0A (ADSEL0A): Selects the register to which the result of multi-
trigger A/D conversion is transferred.
This bit is inverted when the ADDR register is updated by the multi-trigger A/D conversion.
Switching settings during the multi-trigger A/D conversion operation should be carried out
when TADF0A (ADTSR0 register) is set to 1.
Bit 0:
ADSEL0A
0
1
Description
Conversion result is transferred to ADDR8
Conversion result is transferred to ADDR9
(Initial value)
18.2.2 A/D Trigger Status Registers 0 and 1 (ADTSR0 and ADTSR1)
A/D trigger status registers 0 and 1 (ADTSR0 and ADTSR1) indicate the compare match
generation and the multi-trigger A/D conversion status in channels 0 and 1.
ADTSR0 and ADTSR1 are initialized to H'00 by a power-on reset, and in hardware standby mode
and software standby mode.
Bit:
7
6
5
4
TADFxB TADFxA ADDFxB
Initial value:
0
R/W:
0
R/(W)*
0
R/(W)*
0
R/(W)*
Note: x = 0 or 1.
* Only 0 can be written, to clear the flag.
3
2
1
0
ADDFxA ADCYLFx ADCMFxB ADCMFxA
0
R/(W)*
0
R/(W)*
0
R/(W)*
0
R/(W)*
Rev. 3.0, 09/04, page 657 of 1086