SH7058 Datasheet, PDF (184/1130 Pages) Renesas Technology Corp – Renesas SuperHTM RISC engine

9.1.3 Pin Configuration
Table 9.1 shows the bus state controller pin configuration.
Table 9.1 Pin Configuration
Name
Abbr.
I/O Description
Address bus
A21–A0
O
Address output
Data bus
D15–D0
I/O 16-bit data bus
Chip select
CS0–CS3 O
Chip select signals indicating the area being
accessed
Read
RD
O
Strobe that indicates the read cycle for ordinary
space/multiplex I/O
Upper write
WRH
O
Strobe that indicates a write cycle to the upper 8 bits
(D15–D8)
Lower write
WRL
O
Strobe that indicates a write cycle to the lower 8 bits
(D7–D0)
Wait
WAIT
I
Wait state request signal
Bus request
BREQ
I
Bus release request input
Bus acknowledge BACK
O
Bus use enable output
Notes: 1. When an 8-bit bus width is selected for external space, WRL is enabled.
2. When a 16-bit bus width is selected for external space, WRH and WRL are enabled.
9.1.4 Register Configuration
The BSC has four registers. These registers are used to control wait states, bus width, and
interfaces with memories like ROM and SRAM, as well as refresh control. The register
configurations are listed in table 9.2.
All registers are 16 bits. All BSC registers are all initialized by a power-on reset and in hardware
standby mode. Values are retained in a manual reset and in software standby mode.
Table 9.2 Register Configuration
Name
Abbr. R/W Initial Value Address Access Size
Bus control register 1
BCR1 R/W H'000F
H'FFFFEC20 8, 16, 32
Bus control register 2
BCR2 R/W H'FFFF
H'FFFFEC22 8, 16, 32
Wait state control register
WCR
R/W H'7777
H'FFFFEC24 8, 16, 32
RAM emulation register
RAMER R/W H'0000
H'FFFFEC26 8, 16, 32
Note: In register access, four cycles are required for byte access and word access, and eight
cycles for longword access.
Rev. 3.0, 09/04, page 143 of 1086