SH7058 Datasheet, PDF (311/1130 Pages) Renesas Technology Corp – Renesas SuperHTM RISC engine

• Bit 15—Reserved: This bit is always read as 0. The write value should always be 0.
• Bit 14—Overflow Flag 5 (OVF5): Status flag that indicates TCNT5 overflow.
Bit 14: OVF5
0
1
Description
[Clearing condition]
When OVF5 is read while set to 1, then 0 is written to OVF5
[Setting condition]
When the TCNT5 value overflows (from H'FFFF to H'0000)
(Initial value)
• Bit 13—Input Capture/Compare-Match Flag 5D (IMF5D): Status flag that indicates GR5D
input capture or compare-match.
Bit 13: IMF5D
0
1
Description
[Clearing condition]
(Initial value)
When IMF5D is read while set to 1, then 0 is written to IMF5D
[Setting conditions]
• When the TCNT5 value is transferred to GR5D by an input capture signal
while GR5D is functioning as an input capture register
• When TCNT5 = GR5D while GR5D is functioning as an output compare
register
• When TCNT5 = GR5D while GR5D is functioning as a cycle register in
PWM mode
• Bit 12—Input Capture/Compare-Match Flag 5C (IMF5C): Status flag that indicates GR5C
input capture or compare-match. The flag is not set in PWM mode.
Bit 12: IMF5C
0
1
Description
[Clearing condition]
(Initial value)
When IMF5C is read while set to 1, then 0 is written to IMF5C
[Setting conditions]
• When the TCNT5 value is transferred to GR5C by an input capture signal
while GR5C is functioning as an input capture register
• When TCNT5 = GR5C while GR5C is functioning as an output compare
register
Rev. 3.0, 09/04, page 270 of 1086