SH7058 Datasheet, PDF (986/1130 Pages) Renesas Technology Corp – Renesas SuperHTM RISC engine

25.1.2 Pin Configuration
Pins related to power-down modes are shown in table 25.2.
Table 25.2 Pin Configuration
Pin Name
Hardware standby input pin
Abbreviation
HSTBY
Power-on reset input pin
RES
I/O
Input
Input
Function
Input level determines transition to
hardware standby mode
Power-on reset signal input pin
25.1.3 Related Registers
Table 25.3 shows the registers used for power-down state control.
Table 25.3 Related Registers
Name
Initial
Abbreviation R/W Value Write
Address
Read
Access
Size
Standby control register SBYCR^*1
R/W H'1F
H'FFFFEC14
8
System control register 1 SYSCR1^*1 R/W H'01
H'FFFFF708
8
System control register 2 SYSCR2^*1 R/W H'01 H'FFFFF70A^*2 H'FFFFF70B^*3 8, 16
Notes: 1. Register access with an internal clock multiplication ratio of 4 requires four internal
clock (φ) cycles for SBYCR, and four or five internal clock (φ) cycles for SYSCR1 and
SYSCR2.
2. Write data in words. Data cannot be written in bytes or longwords.
3. Read data in bytes. Values cannot be read correctly if data is read in words or
longwords.
25.2 Register Descriptions
25.2.1 Standby Control Register (SBYCR)
The standby control register (SBYCR) is an 8-bit readable/writable register that sets the transition
to standby mode, and the port state in standby mode. SBYCR is initialized to H'1F by a power-on
reset.
Rev. 3.0, 09/04, page 945 of 1086