SH7058 Datasheet, PDF (38/1130 Pages) Renesas Technology Corp – Renesas SuperHTM RISC engine

22.10.2 Port J Data Register (PJDR)................................................................................. 824
22.10.3 Port J Port Register (PJPR) .................................................................................. 825
22.11 Port K................................................................................................................................ 826
22.11.1 Register Configuration......................................................................................... 826
22.11.2 Port K Data Register (PKDR) .............................................................................. 827
22.12 Port L ................................................................................................................................ 828
22.12.1 Register Configuration......................................................................................... 828
22.12.2 Port L Data Register (PLDR)............................................................................... 829
22.12.3 Port L Port Register (PLPR) ................................................................................ 830
22.13 POD (Port Output Disable) Control.................................................................................. 831
Section 23 ROM ................................................................................................833
23.1 Features ............................................................................................................................. 833
23.2 Overview........................................................................................................................... 835
23.2.1 Block Diagram ..................................................................................................... 835
23.2.2 Operating Mode ................................................................................................... 836
23.2.3 Mode Comparison................................................................................................ 838
23.2.4 Flash Memory Configuration............................................................................... 839
23.2.5 Block Division ..................................................................................................... 840
23.2.6 Programming/Erasing Interface ........................................................................... 841
23.3 Pin Configuration.............................................................................................................. 843
23.4 Register Configuration...................................................................................................... 843
23.4.1 Registers............................................................................................................... 843
23.4.2 Programming/Erasing Interface Registers ........................................................... 846
23.4.3 Programming/Erasing Interface Parameters ........................................................ 851
23.4.4 RAM Emulation Register (RAMER)................................................................... 862
23.5 On-Board Programming Mode ......................................................................................... 864
23.5.1 Boot Mode ........................................................................................................... 864
23.5.2 User Program Mode............................................................................................. 868
23.5.3 User Boot Mode................................................................................................... 878
23.6 Protection .......................................................................................................................... 881
23.6.1 Hardware Protection ............................................................................................ 881
23.6.2 Software Protection.............................................................................................. 882
23.6.3 Error Protection.................................................................................................... 883
23.7 Flash Memory Emulation in RAM ................................................................................... 885
23.8 Usage Notes ...................................................................................................................... 888
23.8.1 Switching between User MAT and User Boot MAT........................................... 888
23.8.2 Interrupts during Programming/Erasing .............................................................. 889
23.8.3 Other Notes .......................................................................................................... 893
23.9 Programmer Mode ............................................................................................................ 894
23.9.1 Pin Arrangement of Socket Adapter .................................................................... 895
23.9.2 Programmer Mode Operation .............................................................................. 897
23.9.3 Memory-Read Mode............................................................................................ 898
Rev. 3.0, 09/04, page xxxv of xxxviii