SH7058 Datasheet, PDF (222/1130 Pages) Renesas Technology Corp – Renesas SuperHTM RISC engine

Table 10.2 Selecting On-Chip Peripheral Module Request Modes with the RS Bits (cont)
DMAC
Transfer
Request
RS4 RS3 RS2 RS1 RS0 Source
1
0
0
0
1
ATU-II
1 0 ATU-II
1 ATU-II
1 0 0 ATU-II
1 ATU-II
1 0 ATU-II
1 ATU-II
1
0
0
0
ATU-II
1 ATU-II
1 0 ATU-II
1 ATU-II
1 0 0 ATU-II
DMAC Transfer
Request Signal
ICI0A (ICR0A input
capture generation)
ICI0B (ICR0B input
capture generation)
ICI0C (ICR0C input
capture generation)
ICI0D (ICR0D input
capture generation)
CMI6A (CYLR6A
compare-match
generation)
CMI6B (CYLR6B
compare-match
generation)
CMI6C (CYLR6C
compare-match
generation)
CMI6D (CYLR6D
compare-match
generation)
CMI7A (CYLR7A
compare-match
generation)
CMI7B (CYLR7B
compare-match
generation)
CMI7C (CYLR7C
compare-match
generation)
CMI7D (CYLR7D
compare-match
generation)
Transfer
Source
Transfer
Destination Bus Mode
Don’t care* Don’t care* Burst/cycle-
steal
Don’t care* Don’t care* Burst/cycle-
steal
Don’t care* Don’t care* Burst/cycle-
steal
Don’t care* Don’t care* Burst/cycle-
steal
Don’t care* Don’t care* Burst/cycle-
steal
Don’t care* Don’t care* Burst/cycle-
steal
Don’t care* Don’t care* Burst/cycle-
steal
Don’t care* Don’t care* Burst/cycle-
steal
Don’t care* Don’t care* Burst/cycle-
steal
Don’t care* Don’t care* Burst/cycle-
steal
Don’t care* Don’t care* Burst/cycle-
steal
Don’t care* Don’t care* Burst/cycle-
steal
Rev. 3.0, 09/04, page 181 of 1086