SH7058 Datasheet, PDF (702/1130 Pages) Renesas Technology Corp – Renesas SuperHTM RISC engine

Conversion mode (ADCR): continuous scan
Channels for conversion (ADCSRx):
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Analog Input Channels
ADM1
ADM0
CH3
CH2
CH1
CH0
A/D0
A/D1
0
1
0
0
1
1
AN0 to
AN12 to
AN3
AN15
1
0
0
0
1
1
AN0 to
AN12 to
AN7
AN19
0
1
0
1
1
1
AN4 to
AN16 to
AN7
AN19
Notes: 1. x = 0 or 1.
2. For the ADCR and ADCSRx settings, refer to section 17, A/D Converter.
• Bit 6—Trigger A/D Interrupt Enable B (TADExB): Enables or disables the interrupt request
by TADFxB when the trigger A/D flag xB (TADFxB) in ADTSR is set to 1.
To prevent incorrect operation, ensure that the ADTRG bit in A/D trigger interrupt enable
register (ADTIER0 or ADTIER1) is 0 before switching this setting.
Bit 6: TADExB
0
1
Description
The interrupt request (TADIxB) by TADFxB is disabled
The interrupt request (TADIxB) by TADFxB is enabled
(Initial value)
When multi-trigger A/D conversion B ends, setting TADFxB to 1, a trigger A/D interrupt for
A/D0 or A/D1 (TADIxB) is requested if TADExB is 1. TADIxB can be cleared to 0 by clearing
TADFxB or TADExB to 0.
• Bit 5—Trigger A/D Interrupt Enable A (TADExA): Enables or disables the interrupt request
by TADFxA when the trigger A/D flag xA (TADFxA) in ADTSR is set to 1.
To prevent incorrect operation, ensure that the ADTRG bit in A/D trigger interrupt enable
register (ADTIER0 or ADTIER1) is 0 before switching this setting.
Bit 5: TADExA Description
0
The interrupt request (TADIxA) by TADFxA is disabled
1
The interrupt request (TADIxA) by TADFxA is enabled
(Initial value)
When multi-trigger A/D conversion A ends setting TADFxA to 1, a trigger A/D interrupt for
A/D0 or A/D1 (TADIxA) is requested if TADExA is 1. TADIxA can be cleared to 0 by clearing
TADFxA or TADExA to 0.
Rev. 3.0, 09/04, page 661 of 1086