SH7058 Datasheet, PDF (216/1130 Pages) Renesas Technology Corp – Renesas SuperHTM RISC engine

10.2.5 DMAC Operation Register (DMAOR)
Bit: 15
14
13
12
11
10
9
8
—
—
—
—
—
—
—
—
Initial value: 0
0
0
0
0
0
0
0
R/W: R
R
R
R
R
R
R
R
Bit: 7
6
5
4
3
—
—
—
—
—
Initial value: 0
0
0
0
0
R/W: R
R
R
R
R
Note: * Only a 0 write is valid after 1 is read at the AE and NMIF bits.
2
AE
0
R/(W)*
1
NMIF
0
R/(W)*
0
DME
0
R/W
DMAOR is a 16-bit readable/writable register that controls the overall operation of the DMAC.
Register values are initialized to H'0000 by a power-on reset and in standby mode.
• Bits 15–3—Reserved: These bits are always read as 0. The write value should always be 0.
• Bit 2—Address Error Flag (AE): Indicates that an address error has occurred during DMA
transfer. If this bit is set during a data transfer, transfers on all channels are suspended. The
CPU cannot write a 1 to the AE bit. Clearing is effected by a 0 write after a 1 read.
Bit 2: AE
0
1
Description
No address error, DMA transfer enabled
[Clearing condition]
Write AE = 0 after reading AE = 1
Address error, DMA transfer disabled
[Setting condition]
Address error due to DMAC
(Initial value)
Rev. 3.0, 09/04, page 175 of 1086