SH7058 Datasheet, PDF (865/1130 Pages) Renesas Technology Corp – Renesas SuperHTM RISC engine

22.10.1 Register Configuration
The port J register configuration is shown in table 22.17.
Table 22.17 Register Configuration
Name
Abbreviation R/W Initial Value Address
Access Size
Port J data register PJDR
R/W H'0000
H'FFFFF76C 8, 16
Port J port register PJPR
R
Port J pin
H'FFFFF786 8, 16
values
Note: Register access with an internal clock multiplication ratio of 4 requires four or five internal
clock (φ) cycles.
22.10.2 Port J Data Register (PJDR)
Bit: 15
14
13
12
11
10
9
8
PJ15 PJ14 PJ13 PJ12 PJ11 PJ10 PJ9
PJ8
DR
DR
DR
DR
DR
DR
DR
DR
Initial value: 0
0
0
0
0
0
0
0
R/W: R/W R/W R/W R/W R/W R/W R/W R/W
Bit: 7
6
5
4
3
2
1
0
PJ7
PJ6
PJ5
PJ4
PJ3
PJ2
PJ1
PJ0
DR
DR
DR
DR
DR
DR
DR
DR
Initial value: 0
0
0
0
0
0
0
0
R/W: R/W R/W R/W R/W R/W R/W R/W R/W
The port J data register (PJDR) is a 16-bit readable/writable register that stores port J data. Bits
PJ15DR to PJ0DR correspond to pins PJ15/TI9F to PJ0/TIO2A.
When a pin functions as a general output, if a value is written to PJDR, that value is output
directly from the pin, and if PJDR is read, the register value is returned directly regardless of the
pin state.
When a pin functions as a general input, if PJDR is read, the pin state, not the register value, is
returned directly. If a value is written to PJDR, although that value is written into PJDR, it does
not affect the pin state. Table 22.18 summarizes port J data register read/write operations.
PJDR is initialized to H'0000 by a power-on reset (excluding a WDT power-on reset), and in
hardware standby mode. It is not initialized in software standby mode or sleep mode.
Rev. 3.0, 09/04, page 824 of 1086