SH7058 Datasheet, PDF (601/1130 Pages) Renesas Technology Corp – Renesas SuperHTM RISC engine

Bit
Bit Name Initial Value R/W Description
3
IRR3
0
R/W Transmit Overload Warning Interrupt Flag
This bit is set and latched if the transmit error
counter (TEC) reaches a value greater than 96.
This bit is cleared by writing 1. Writing 0 is
ignored. When the interrupt is cleared, TEC still
holds its value greater than 96.
0: Clearing condition: Writing 1
1: Error warning state caused by transmit error
Setting condition: When TEC ≥ 96
2
IRR2
0
R
Remote Frame Request Interrupt Flag
Indicates that a remote frame has been received
in a mailbox. This bit is set if at least one receive
mailbox contains a remote frame transmission
request. This bit is cleared by ensuring all bits in
the remote request wait register (RFPR) are
cleared. Writing to this bit is ignored.
0: Clearing condition: Clearing of all bits in RFPR
1: At least one remote request is waiting
Setting condition:
When a remote frame is received and the
corresponding MBIMR = 0
1
IRR1
0
R
Data Frame Received Interrupt Flag
Indicates that there are waiting data frames
received. If at least one receive mailbox contains
a waiting message, this bit is set. This bit is
cleared when all bits in the receive message
waiting register (RXPR) are cleared, i.e. there is
no waiting message in any receive mailbox. A
logical OR from each set receive mailbox. Writing
to this bit is ignored.
0: Clearing condition: Clearing of all bits in RXPR
1: Data frame received and stored in mailbox
Setting condition: When data is received and
the corresponding MBIMR = 0
Rev. 3.0, 09/04, page 560 of 1086